14.8.210 DLCA

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-242. DLCA Logic Diagram
  • Function: Data Latch with active low Clear and Clock
  • Input: CLR, D, G
  • Output: Q
Table 14-396. Truth Table
CLRGQn+1
0X0
11Q
10D
Table 14-397. Modules
FamilySeqComb
Others1
ACT 2, 1200XL, ACT 3, 3200DX, MX1