14.8.181 DFME3A

This component is supported by Accelerator family.

Figure 14-213. DFME3A Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Enable and Clear
  • Input: CLK, A, B, S, E, CLR
  • Output: Q
Table 14-338. Truth Table
CLRESCLKQn+1
0XXX0
11XXQ
100A
101B
Table 14-339. Modules
FamilySeqComb
All listed1