14.8.152 DFMEG
This component is supported by Accelerator families.
- Function: D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Enable, Preset, and Clear
- Input: CLK, A, B, S, E, PRE, CLR
- Output: Q
| CLR | PRE | E | S | CLK | Qn+1 |
|---|---|---|---|---|---|
| 0 | X | X | X | X | 0 |
| 1 | 0 | X | X | X | 1 |
| 1 | 1 | 1 | X | X | Q |
| 1 | 1 | 0 | 0 | ↑ | A |
| 1 | 1 | 0 | 1 | ↑ | B |
| Family | Seq | Comb |
|---|---|---|
| All listed | 1 | — |