14.8.234 DLP1

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-268. DLP1 Logic Diagram
  • Function: Data Latch with active high Preset and Clock
  • Input: D, G, PRE
  • Output: Q
Table 14-444. Truth Table
PREGQn+1
1X1
00Q
01D
Table 14-445. Modules
FamilySeqComb
All1