14.8.232 DLMA

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-266. DLMA Logic Diagram
  • Function: Data Latch with 2-input Multiplexed Data and active low Clock
  • Input: A, B, G, S
  • Output: Q
Table 14-440. Truth Table
SGQn+1
X1Q
00A
10B
Table 14-441. Modules
FamilySeqComb
ACT 1/MX—1
Others1—