14.8.180 DFME2B

This component is supported by Accelerator family.

Figure 14-212. DFME2B Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable and Preset
  • Input: CLK, A, B, S, E, PRE
  • Output: Q
Table 14-336. Truth Table
PREESCLKQn+1
0XXX1
11XXQ
100A
101B
Table 14-337. Modules
FamilySeqComb
All listed1