14.8.202 DL2B
This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX families.
- Function: Data Latch with active high Clear and active low Preset, Clock, and Output
- Input: CLR, D, G, PRE
- Output: QN
| CLR | PRE | G | QNn+1 |
|---|---|---|---|
| 1 | 1 | X | 1 |
| 0 | 0 | X | 0 |
| 0 | 1 | 1 | QN |
| 0 | 1 | 0 | !D |
| 1 | 0 | X | * |
| Family | Seq | Comb |
|---|---|---|
| ACT 1/MX | — | 1 |
| Others | — | 2 |
Note: * In ACT 1 and MX, your design should not allow PRE and CLR to be asserted at the same time. In other families, CLR has priority over PRE.