14.8.212 DLE1D

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-244. DLE1D Logic Diagram
  • Function: Data Latch with active low Enable and Clock and active low Output
  • Input: D, E, G
  • Output: QN
Table 14-400. Truth Table
EGQNn+1
1XQN
X1QN
00!D
Table 14-401. Modules
FamilySeqComb
ACT 1/MX—1
Others1—