14.8.235 DLP1A

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-269. DLP1A Logic Diagram
  • Function: Data Latch with active high Preset and active low Clock
  • Input: D, G, PRE
  • Output: Q
Table 14-446. Truth Table
PREGQn+1
1X1
01Q
00D
Table 14-447. Modules
FamilySeqComb
All—1