14.8.194 DFPCA

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX families.

Figure 14-226. DFPCA Logic Diagram
  • Function: D-Type Flip-Flop with active high Preset, active low Clear and Clock
  • Input: CLR, D, PRE, CLK
  • Output: Q
Table 14-364. Truth Table
CLRPRECLKQn+1
00X0
11X1
10↓D
01X*
Table 14-365. Modules
FamilySeqComb
All—2
Note: * Your design should not allow both PRE and CLR to be asserted at the same time.