14.8.193 DFPC
This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.
- Function: D-Type Flip-Flop with active high Preset, active low Clear, and active high Clock
- Input: CLR, D, PRE, CLK
- Output: Q
| CLR | PRE | CLK | Qn+1 |
|---|---|---|---|
| 0 | 0 | X | 0 |
| 1 | 1 | X | 1 |
| 1 | 0 | ↑ | D |
| 0 | 1 | X | ** |
| Family | Seq | Comb |
|---|---|---|
| Others | 1 | 1 |
| ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S | — | 2 |
Note: * A 2 on the symbol implies 2 logic module delays only for SX, SX-A, SX-S, and eX.
Note: ** In ACT 1/MX, your design should not allow both PRE and CLR to be asserted at the same time. In other families, CLR has priority over PRE.