14.8.209 DLC1G

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-241. DLC1G Logic Diagram
  • Function: Data Latch with active high Clear and active low Clock and Output
  • Input: CLR, D, G
  • Output: QN
Table 14-394. Truth Table
CLRGQNn+1
1X1
01QN
00!D
Table 14-395. Modules
FamilySeqComb
ACT 1/MX1
Others2