14.8.252 GOR2

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-286. GOR2 Logic Diagram
  • Function: 2-Input OR Clock Net
  • Input: A, G
  • Output: Y
Table 14-478. Truth Table
AGY
000
X11
1X1
Table 14-479. Modules
FamilySeqComb
All—1
Note: G pin can be connected directly to a routed clock (RCLK) if supported by your device. See your device datasheet for more information.