14.8.204 DL2D

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX families.

Figure 14-236. DL2D Logic Diagram
  • Function: Data Latch with active high Clear and active low Preset and Output
  • Input: CLR, D, G, PRE
  • Output: QN
Table 14-384. Truth Table
CLRPREGQNn+1
11X1
00X0
010QN
011!D
10X*
Table 14-385. Modules
FamilySeqComb
ACT 1/MX1
Others2
Note: * In ACT 1 and MX, your design should not allow PRE and CLR to be asserted at the same time. In other families, CLR has priority over PRE.