14.8.148 IODFE

This component is supported by ACT 3 families.

Figure 14-176. IODFE Logic Diagram
  • Function: D-Type Flip-Flop with active low Enable
  • Input: D, E, CLK
  • Output: Q
Table 14-275. Truth Table
ECLKQn+1
1XQ
0↑D
Note: The CLK pin must be driven by the IOCLKBUF macro.
Warning: Using the IODFE macro will disable the IOPCLBUF clock network.
Note: Uses an I/O module.