14.8.153 DFMEH

This component is supported by Accelerator family.

Figure 14-181. DFMEH Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable, Preset, and Clear
  • Input: CLK, A, B, S, E, PRE, CLR
  • Output: Q
Table 14-282. Truth Table
CLRPREESCLKQn+1
0XXXX0
10XXX1
111XXQ
1100A
1101B
Table 14-283. Modules
FamilySeqComb
All listed1