14.8.144 DFEC

This component is supported by ACT 1, MX families.

Figure 14-172. DFEC Logic Diagram
  • Function: D-Type Flip-Flop with Enable, Preset, and active low Clear and Clock
  • Input: CLR, D, E, PRE, CLK
  • Output: Q
Table 14-267. Truth Table
CLRPREECLKQn+1
00XX0
11XX1
100XQ
101D
01XX*
Table 14-268. Modules
FamilySeqComb
ACT 1/MX2
Note: Your design should not allow both PRE and CLR to be asserted at the same time.