14.8.196 DFPCC

This component is supported by SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-228. DFPCC Logic Diagram
  • Function: D-Type Flip-Flop with active low Preset, Clear and Clock
  • Input: CLR, D, PRE, CLK
  • Output: Q
Table 14-368. Truth Table
CLRPRECLKQn+1
0XX0
10X1
11D
Table 14-369. Modules
FamilySeqComb
All listed1