14.8.121 DFC1A

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX families.

Figure 14-149. DFC1A Logic Diagram
  • Function: D-Type Flip-Flop with active high Clear and active low Clock
  • Input: CLR, D, CLK
  • Output: Q
Table 14-221. Truth Table
CLRCLKQn+1
1X0
0D
Table 14-222. Modules
FamilySeqComb
ACT 1, MX2
Others11
Note: A 2 on the symbol implies 2 logic module delays on all families except ACT1 and MX.