14.8.248 GMX4

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-282. GMX4 Logic Diagram
  • Function: 4-to-1 Mux Clock Net
  • Input: D0, D1, D2, D3, S0, G
  • Output: Y
Table 14-472. Truth Table
GS0Y
00D0
01D1
10D2
11D3
Table 14-473. Modules
FamilySeqComb
All1
Note: G pin can be connected directly to a routed clock (RCLK) or hardwired clock (HCLK) if supported by your device. See your device datasheet for more info.