14.8.229 DLM4A

This component is supported by ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-261. DLM4A Logic Diagram
  • Function: Data Latch with 4-input Multiplexed Data and active low Clock
  • Input: D0, D1, D2, D3, S0, S10, S11, G
  • Output: Q
Table 14-434. Truth Table
S10S11S0GQn+1
XXX1Q
0000D0
0010D1
X100D2
1X00D2
X110D3
1X10D3
Table 14-435. Modules
FamilySeqComb
All listed1