14.8.207 DLC1A

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-239. DLC1A Logic Diagram

Function: Data Latch with active high Clear and active low Clock
Input: CLR, D, G
Output: Q

Table 14-390. Truth Table
CLR	G	Qn+1
1	X	0
0	1	Q
0	0	D

Table 14-391. Modules
Family	Seq	Comb
All	—	1

Rev: A