14.8.219 DLEA

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-251. DLEA Logic Diagram
  • Function: Data Latch with active low Enable and active high Clock
  • Input: D, E, G
  • Output: Q
Table 14-414. Truth Table
EGQn+1
1XQ
X0Q
01D
Table 14-415. Modules
FamilySeqComb
ACT 1/MX—1
Others1—