14.8.272 JKFPC

This component is supported by ACT 1, MX families.

Figure 14-306. JKFPC Logic Diagram
  • Function: JK Flip-Flop with active high Preset, and active low Clear and K-Input
  • Input: CLR, J, K, PRE, CLK
  • Output: Q
Table 14-518. Truth Table
CLRPREJKCLKQn+1
00XXX0
11XXX1
1000↑0
1001↑Q
1010↑!Q
1011↑1
01XXX*
Table 14-519. Modules
FamilySeqComb
ACT 1/MX—2
Note: * Your design should not allow both PRE and CLR to be asserted at the same time.