14.8.175 DFMA

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-207. DFMA Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clock
  • Input: A, B, S, CLK
  • Output: Q
Table 14-326. Truth Table
SCLKQn+1
0↓A
1↓B
Table 14-327. Modules
FamilySeqComb
ACT 1/MX—2
Others1—