14.8.238 DLP1D

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-272. DLP1D Logic Diagram
  • Function: Data Latch with active low Preset and Output, and active high Clock
  • Input: D, G, PRE
  • Output: QN
Table 14-452. Truth Table
PREGQNn+1
0X0
10QN
11!D
Table 14-453. Modules
FamilySeqComb
ACT 1/MX—1
Others1—