14.8.126 DFC1F

This component is supported by ACT 1, MX families.

Figure 14-154. DFC1F Logic Diagram
  • Function: D-Type Flip-Flop with active high Clear, active low Clock and Output
  • Input: CLR, D, CLK
  • Output: QN
Table 14-231. Truth Table
CLRCLKQNn+1
1X1
0!D
Table 14-232. Modules
FamilySeqComb
ACT 1, MX2