14.8.168 DFM5B

This component is supported by ACT 1, MX families.

Figure 14-196. DFM5B Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, Preset, and active low Clear and Clock
  • Input: A, B, CLR, PRE, S, CLK
  • Output: Q
Table 14-312. Truth Table
CLRPRESCLKQn+1
00XX0
11XX1
100A
101B
01XX*
Table 14-313. Modules
FamilySeqComb
All listed2
Note: Your design should not allow both PRE and CLR to be asserted at the same time.