14.8.178 DFME1B

This component is supported by Accelerator family.

Figure 14-210. DFME1B Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable
  • Input: CLK, A, B, S, E
  • Output: Q
Table 14-332. Truth Table
ESCLKQn+1
1XXQ
00A
01B
Table 14-333. Modules
FamilySeqComb
All listed1