14.8.247 GAND2

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Accelerator families.

Figure 14-281. GAND2 Logic Diagram
  • Function: 2-Input AND Clock Net
  • Input: A, G
  • Output: Y
Table 14-470. Truth Table
AGY
X00
0X0
111
Table 14-471. Modules
FamilySeqComb
All1
Note: G pin can be connected directly to a routed clock (RCLK) or hardwired clock (HCLK) if supported by your device. See your device datasheet for more info.