14.8.216 DLE3A

This component is supported by ACT 1, MX families.

Figure 14-248. DLE3A Logic Diagram
  • Function: Data Latch with active high Enable and Preset, and active low Clock
  • Input: D, E, G, PRE
  • Output: Q
Table 14-408. Truth Table
PREEGQn+1
1XX1
00XQ
010D
0X1Q
Table 14-409. Modules
FamilySeqComb
ACT 1/MX1