Contents
Features
2. Configuration Summary
3. Ordering Information
4. Block Diagram
5. Pinouts
5.1. Multiplexed Signals
5.2. Oscillators Pinout
5.3. Serial Wire Debug Interface Pinout
5.4. General Purpose I/O (GPIO) Clusters
6. Signal Descriptions List
7. Power Considerations
7.1. Power Supplies
7.2. Power Supply Constraints
7.3. Power-On Reset and Brown-Out Detectors
7.4. Voltage Regulators
7.5. Typical Powering Schematic
8. Analog Peripherals Considerations
8.1. Reference Voltages
8.2. Analog On Demand Feature
9. Device Startup
9.1. Clocks Startup
9.2. Initial Instructions Fetching
9.3. I/O Pins
9.4. Performance Level Overview
10. Product Mapping
11. Memories
11.1. Embedded Memories
11.1.1. Flash
11.1.2. Data Flash
11.1.3. SRAM
11.1.4. TrustRAM
11.1.5. Boot ROM
11.2. NVM Rows
11.2.1. NVM User Row (UROW)
11.2.1.1. SAM L10 User Row
11.2.1.2. SAM L11 User Row
11.2.2. NVM Software Calibration Row
11.2.3. NVM Temperature Log Row
11.2.4. NVM Boot Configuration Row (BOCOR)
11.2.4.1. SAM L10 Boot Configuration Row
11.2.4.2. SAM L11 Boot Configuration Row
11.3. Serial Number
12. Processor and Architecture
12.1. Cortex-M23 Processor
12.1.1. Cortex-M23 Configuration
12.1.2. Cortex-M23 Core Peripherals
12.1.3. Single Cycle I/O Port
12.2. Nested Vector Interrupt Controller
12.2.1. Overview
12.2.2. Interrupt Line Mapping
12.3. High-Speed Bus System
12.3.1. Features
12.3.2. Configuration
12.4. SRAM Quality of Service
13. Peripherals Configuration Summary
14. SAM L11 Specific Security Features
14.1. Features
14.2. Arm TrustZone Technology for Armv8-M
14.2.1. Memory System and Memory Partitioning
14.2.2. Memories Security Attribution
14.2.2.1. Flash
14.2.2.2. Data Flash
14.2.2.3. SRAM
14.2.3. SAM L11 Memory Mapping Configuration Summary
14.2.4. SAM L11 IDAU Memory Mapping Registers
14.2.5. Peripherals Security Attribution
14.2.5.1. SAM L11 Peripherals Configuration Example
14.2.6. SAM L11 Memory Space Security Attribution
14.2.7. Cortex-M23 Test Target Instructions
14.2.8. Mix-Secure Peripherals
14.3. Crypto Acceleration
14.3.1. Overview
14.3.2. Features
14.3.3. CRYA APIs
14.3.3.1. AES API
14.3.3.2. SHA API
14.3.3.3. GCM API
14.4. Secure Boot
14.5. Secure Pin Multiplexing on SERCOM
14.6. Data Flash Scrambling
15. Boot ROM
15.1. Features
15.2. Block Diagram
15.3. Product Dependencies
15.3.1. Clocks
15.3.2. NVM User (UROW) and Boot Configuration (BOCOR) rows
15.3.3. Debug Operations
15.4. Functional Description
15.4.1. SAM L10 Boot ROM Flow
15.4.2. SAM L11 Boot ROM Flow
15.4.3. Debug Access Levels
15.4.4. Chip Erase
15.4.5. Boot ROM Interactive Mode
15.4.6. CPU Park mode
16. PAC - Peripheral Access Controller
16.1. Overview
16.2. Features
16.3. Block Diagram
16.4. Product Dependencies
16.4.1. IO Lines
16.4.2. Power Management
16.4.3. Clocks
16.4.4. DMA
16.4.5. Interrupts
16.4.6. Events
16.4.7. Debug Operation
16.4.8. Register Access Protection
16.4.9. SAM L11 TrustZone Specific Register Access Protection
16.5. Functional Description
16.5.1. Principle of Operation
16.5.2. Basic Operation
16.5.2.1. Initialization
16.5.2.2. Initialization, Enabling and Resetting
16.5.2.3. Operations
16.5.2.4. Peripheral Access Errors
16.5.2.5. Write Access Protection Management
16.5.2.6. Write Access Protection Management Errors
16.5.2.7. SAM L11 Security Attribution Management
16.5.2.8. SAM L11 Security Attribution Management Errors
16.5.2.9. AHB Client Bus Errors
16.5.2.10. Generating Events
16.5.3. DMA Operation
16.5.4. Interrupts
16.5.5. Events
16.5.6. Sleep Mode Operation
16.5.7. SAM L11 Secure and Non-Secure Read/Write Accesses
16.5.8. Synchronization
16.6. Register Summary
16.7. Register Description
16.7.1. Write Control
16.7.2. Event Control
16.7.3. Interrupt Enable Clear
16.7.4. Interrupt Enable Set
16.7.5. AHB Client Bus Interrupt Flag Status and Clear
16.7.6. Peripheral Interrupt Flag Status and Clear A
16.7.7. Peripheral Interrupt Flag Status and Clear B
16.7.8. Peripheral Interrupt Flag Status and Clear C
16.7.9. Peripheral Write Protection Status A
16.7.10. Peripheral Write Protection Status B
16.7.11. Peripheral Write Protection Status C
16.7.12. Peripheral Non-Secure Status - Bridge A
16.7.13. Peripheral Non-Secure Status - Bridge B
16.7.14. Peripheral Non-Secure Status - Bridge C
17. Device Service Unit (DSU)
17.1. Overview
17.2. Features
17.3. Block Diagram
17.4. Signal Description
17.5. Product Dependencies
17.5.1. I/O Lines
17.5.2. Power Management
17.5.3. Clocks
17.5.4. DMA
17.5.5. Interrupts
17.5.6. Events
17.5.7. Register Access Protection
17.5.8. SAM L11 TrustZone-Specific Register Access Protection
17.5.9. Analog Connections
17.6. Debug Operation
17.6.1. Principle of Operation
17.6.2. CPU Reset Extension
17.6.3. Debugger Probe Detection
17.6.3.1. Cold Plugging
17.6.3.2. Hot Plugging
17.6.4. Boot Communication Channels
17.7. Programming
17.8. Security Enforcement
17.9. Device Identification
17.9.1. CoreSight Identification
17.9.2. Chip Identification Method
17.10. Functional Description
17.10.1. Principle of Operation
17.10.2. Basic Operation
17.10.2.1. Initialization
17.10.2.2. Operation From a Debug Adapter
17.10.2.3. Operation From the CPU
17.10.3. 32-bit Cyclic Redundancy Check CRC32
17.10.3.1. Starting CRC32 Calculation
17.10.3.2. Interpreting the Results
17.10.4. Debug Communication Channels
17.10.5. Boot Communication Channels
17.10.6. Testing of On-Board Memories MBIST
17.10.7. System Services Availability when Accessed Externally
17.11. Register Summary
17.12. Register Description
17.12.1. Control
17.12.2. Status A
17.12.3. Status B
17.12.4. Address
17.12.5. Length
17.12.6. Data
17.12.7. Debug Communication Channel 0
17.12.8. Debug Communication Channel 1
17.12.9. Device Identification
17.12.10. Configuration
17.12.11. Boot Communication Channel 0
17.12.12. Boot Communication Channel 1
17.12.13. CoreSight ROM Table Entry 0
17.12.14. CoreSight ROM Table Entry 1
17.12.15. CoreSight ROM Table End
17.12.16. CoreSight ROM Table Memory Type
17.12.17. Peripheral Identification 4
17.12.18. Peripheral Identification 0
17.12.19. Peripheral Identification 1
17.12.20. Peripheral Identification 2
17.12.21. Peripheral Identification 3
17.12.22. Component Identification 0
17.12.23. Component Identification 1
17.12.24. Component Identification 2
17.12.25. Component Identification 3
18. Clock System
18.1. Clock Distribution
18.2. Synchronous and Asynchronous Clocks
18.3. Register Synchronization
18.3.1. Overview
18.3.2. General Write Synchronization
18.3.3. General Read Synchronization
18.3.4. Completion of Synchronization
18.3.5. Write Synchronization for CTRLA.ENABLE
18.3.6. Write-Synchronization for Software Reset Bit
18.3.7. Synchronization Delay
18.4. Enabling a Peripheral
18.5. On Demand Clock Requests
18.6. Power Consumption vs. Speed
18.7. Clocks after Reset
19. GCLK - Generic Clock Controller
19.1. Overview
19.2. Features
19.3. Block Diagram
19.4. Signal Description
19.5. Product Dependencies
19.5.1. I/O Lines
19.5.2. Power Management
19.5.3. Clocks
19.5.4. DMA
19.5.5. Interrupts
19.5.6. Events
19.5.7. Debug Operation
19.5.8. Register Access Protection
19.5.9. SAM L11 TrustZone-Specific Register Access Protection
19.5.10. Analog Connections
19.6. Functional Description
19.6.1. Principle of Operation
19.6.2. Basic Operation
19.6.2.1. Initialization
19.6.2.2. Enabling, Disabling, and Resetting
19.6.2.3. Generic Clock Generator
19.6.2.4. Enabling a Generator
19.6.2.5. Disabling a Generator
19.6.2.6. Selecting a Clock Source for the Generator
19.6.2.7. Changing the Clock Frequency
19.6.2.8. Duty Cycle
19.6.2.9. External Clock
19.6.3. Peripheral Clock
19.6.3.1. Enabling a Peripheral Clock
19.6.3.2. Disabling a Peripheral Clock
19.6.3.3. Selecting the Clock Source for a Peripheral
19.6.3.4. Configuration Lock
19.6.4. Additional Features
19.6.4.1. Peripheral Clock Enable after Reset
19.6.5. Sleep Mode Operation
19.6.5.1. SleepWalking
19.6.5.2. Minimize Power Consumption in Standby
19.6.5.3. Entering Standby Mode
19.6.6. Synchronization
19.7. Register Summary
19.8. Register Description
19.8.1. Control A
19.8.2. Synchronization Busy
19.8.3. Generator Control
19.8.4. Peripheral Channel Control
20. MCLK – Main Clock
20.1. Overview
20.2. Features
20.3. Block Diagram
20.4. Signal Description
20.5. Product Dependencies
20.5.1. I/O Lines
20.5.2. Power Management
20.5.3. Clocks
20.5.3.1. Main Clock
20.5.3.2. CPU Clock
20.5.3.3. APBx and AHBx Clock
20.5.3.4. Clock Domains
20.5.4. DMA
20.5.5. Interrupts
20.5.6. Events
20.5.7. Debug Operation
20.5.8. Register Access Protection
20.5.9. SAM L11 TrustZone-Specific Register Access Protection
20.5.10. Analog Connections
20.6. Functional Description
20.6.1. Principle of Operation
20.6.2. Basic Operation
20.6.2.1. Initialization
20.6.2.2. Enabling, Disabling, and Resetting
20.6.2.3. Selecting the Main Clock Source
20.6.2.4. Selecting the Synchronous Clock Division Ratio
20.6.2.5. Clock Ready Flag
20.6.2.6. Peripheral Clock Masking
20.6.3. DMA Operation
20.6.4. Interrupts
20.6.5. Events
20.6.6. Sleep Mode Operation
20.7. Register Summary
20.8. Register Description
20.8.1. Control A
20.8.2. Interrupt Enable Clear
20.8.3. Interrupt Enable Set
20.8.4. Interrupt Flag Status and Clear
20.8.5. CPU Clock Division
20.8.6. AHB Mask
20.8.7. APBA Mask
20.8.8. APBB Mask
20.8.9. APBC Mask
21. FREQM – Frequency Meter
21.1. Overview
21.2. Features
21.3. Block Diagram
21.4. Signal Description
21.5. Product Dependencies
21.5.1. I/O Lines
21.5.2. Power Management
21.5.3. Clocks
21.5.4. DMA
21.5.5. Interrupts
21.5.6. Events
21.5.7. Debug Operation
21.5.8. Register Access Protection
21.5.9. SAM L11 TrustZone-Specific Register Access Protection
21.6. Functional Description
21.6.1. Principle of Operation
21.6.2. Basic Operation
21.6.2.1. Initialization
21.6.2.2. Enabling, Disabling and Resetting
21.6.2.3. Measurement
21.6.3. DMA Operation
21.6.4. Interrupts
21.6.5. Events
21.6.6. Sleep Mode Operation
21.6.7. Synchronization
21.7. Register Summary
21.8. Register Description
21.8.1. Control A
21.8.2. Control B
21.8.3. Configuration A
21.8.4. Interrupt Enable Clear
21.8.5. Interrupt Enable Set
21.8.6. Interrupt Flag Status and Clear
21.8.7. Status
21.8.8. Synchronization Busy
21.8.9. Value
22. RSTC – Reset Controller
22.1. Overview
22.2. Features
22.3. Block Diagram
22.4. Signal Description
22.5. Product Dependencies
22.5.1. I/O Lines
22.5.2. Power Management
22.5.3. Clocks
22.5.4. DMA
22.5.5. Interrupts
22.5.6. Events
22.5.7. Debug Operation
22.5.8. Register Access Protection
22.5.9. SAM L11 TrustZone-Specific Register Access Protection
22.5.10. Analog Connections
22.6. Functional Description
22.6.1. Principle of Operation
22.6.2. Basic Operation
22.6.2.1. Initialization
22.6.2.2. Enabling, Disabling, and Resetting
22.6.2.3. Reset Causes and Effects
22.6.3. Additional Features
22.6.4. DMA Operation
22.6.5. Interrupts
22.6.6. Events
22.6.7. Sleep Mode Operation
22.7. Register Summary
22.8. Register Description
22.8.1. Reset Cause
23. PM – Power Manager
23.1. Overview
23.2. Features
23.3. Block Diagram
23.4. Signal Description
23.5. Product Dependencies
23.5.1. I/O Lines
23.5.2. Clocks
23.5.3. DMA
23.5.4. Interrupts
23.5.5. Events
23.5.6. Debug Operation
23.5.7. Register Access Protection
23.5.8. SAM L11 TrustZone-Specific Register Access Protection
23.5.9. Analog Connections
23.6. Functional Description
23.6.1. Terminology
23.6.1.1. Performance Levels
23.6.1.1.1. PL0
23.6.1.1.2. PL2
23.6.1.2. Power Domains
23.6.1.2.1. PDSW - Power Domain Switchable
23.6.1.2.2. PDAO - Power Domain Always On
23.6.1.3. Sleep Modes
23.6.1.4. Power Domain States and Gating
23.6.2. Principle of Operation
23.6.3. Basic Operation
23.6.3.1. Initialization
23.6.3.2. Enabling, Disabling and Resetting
23.6.3.3. Sleep Mode Controller
23.6.3.3.1. IDLE Mode
23.6.3.3.2. STANDBY Mode
23.6.3.3.3. OFF Mode
23.6.3.4. Performance Level
23.6.3.5. Power Domain Controller
23.6.3.6. Regulators, RAMs, and NVM State in Sleep Mode
23.6.4. Advanced Features
23.6.4.1. Power Domain Configuration
23.6.4.2. RAM Automatic Low Power Mode
23.6.4.3. SRAM Power Switch Configuration
23.6.4.4. Regulator Automatic Low-Power Mode
23.6.4.5. SleepWalking and Performance Level
23.6.4.6. Wake-Up Time
23.6.5. Standby with Static Power Domain Gating in Details
23.6.6. Sleepwalking with Dynamic Power Domain Gating in Details
23.6.6.1. Dynamic SleepWalking based on Event
23.6.6.2. Dynamic SleepWalking Based on Peripheral DMA Trigger
23.6.7. DMA Operation
23.6.8. Interrupts
23.6.9. Events
23.6.10. Sleep Mode Operation
23.7. Register Summary
23.8. Register Description
23.8.1. Sleep Configuration
23.8.2. Performance Level Configuration
23.8.3. Power Configuration
23.8.4. Interrupt Enable Clear
23.8.5. Interrupt Enable Set
23.8.6. Interrupt Flag Status and Clear
23.8.7. Standby Configuration
24. OSCCTRL – Oscillators Controller
24.1. Overview
24.2. Features
24.3. Block Diagram
24.4. Signal Description
24.5. Product Dependencies
24.5.1. I/O Lines
24.5.2. Power Management
24.5.3. Clocks
24.5.4. DMA
24.5.5. Interrupts
24.5.6. Events
24.5.7. Debug Operation
24.5.8. Register Access Protection
24.5.9. SAM L11 TrustZone-Specific Register Access Protection
24.5.10. Analog Connections
24.6. Functional Description
24.6.1. Principle of Operation
24.6.2. External Multipurpose Crystal Oscillator (XOSC) Operation
24.6.3. Clock Failure Detection Operation
24.6.4. 16MHz Internal Oscillator (OSC16M) Operation
24.6.5. Ultra Low-Power Digital Frequency Locked Loop (DFLLULP) Operation
24.6.5.1. Basic Operation
24.6.5.1.1. Initialization
24.6.5.1.2. Enabling and Disabling
24.6.5.1.3. Closed Loop Mode
24.6.5.1.4. Binary Search
24.6.5.1.5. Dithering
24.6.6. Event Triggered Tuning
24.6.7. Digital Phase Locked Loop (DPLL) Operation
24.6.7.1. Basic Operation
24.6.7.1.1. Initialization, Enabling, Disabling, and Resetting
24.6.7.1.2. Reference Clock Switching
24.6.7.1.3. Output Clock Prescaler
24.6.7.1.4. Loop Divider Ratio Updates
24.6.7.1.5. Digital Filter Selection
24.6.8. DMA Operation
24.6.9. Interrupts
24.6.10. Events
24.6.11. Synchronization
24.7. Register Summary
24.8. Register Description
24.8.1. Event Control
24.8.2. Interrupt Enable Clear
24.8.3. Interrupt Enable Set
24.8.4. Interrupt Flag Status and Clear
24.8.5. Status
24.8.6. External Multipurpose Crystal Oscillator (XOSC) Control
24.8.7. Clock Failure Detector Prescaler
24.8.8. 16MHz Internal Oscillator (OSC16M) Control
24.8.9. DFLLULP Control
24.8.10. DFLLULP Dither Control
24.8.11. DFLLULP Read Request
24.8.12. DFLLULP Delay Value
24.8.13. DFLLULP Target Ratio
24.8.14. DFLLULP Synchronization Busy
24.8.15. DPLL Control A
24.8.16. DPLL Ratio Control
24.8.17. DPLL Control B
24.8.18. DPLL Prescaler
24.8.19. DPLL Synchronization Busy
24.8.20. DPLL Status
25. OSC32KCTRL – 32KHz Oscillators Controller
25.1. Overview
25.2. Features
25.3. Block Diagram
25.4. Signal Description
25.5. Product Dependencies
25.5.1. I/O Lines
25.5.2. Power Management
25.5.3. Clocks
25.5.4. Interrupts
25.5.5. Events
25.5.6. Debug Operation
25.5.7. Register Access Protection
25.5.8. SAM L11 TrustZone-Specific Register Access Protection
25.5.9. Analog Connections
25.6. Functional Description
25.6.1. Principle of Operation
25.6.2. 32 KHz External Crystal Oscillator (XOSC32K) Operation
25.6.3. Clock Failure Detection Operation
25.6.4. 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation
25.6.5. Watchdog Timer Clock Selection
25.6.6. Real-Time Counter Clock Selection
25.6.7. Interrupts
25.6.8. Events
25.7. Register Summary
25.8. Register Description
25.8.1. Interrupt Enable Clear
25.8.2. Interrupt Enable Set
25.8.3. Interrupt Flag Status and Clear
25.8.4. Status
25.8.5. RTC Clock Selection Control
25.8.6. 32 KHz External Crystal Oscillator (XOSC32K) Control
25.8.7. Clock Failure Detector Control
25.8.8. Event Control
25.8.9. 32KHz Ultra Low-Power Internal Oscillator (OSCULP32K) Control
26. SUPC – Supply Controller
26.1. Overview
26.2. Features
26.3. Block Diagram
26.4. Signal Description
26.5. Product Dependencies
26.5.1. I/O Lines
26.5.2. Power Management
26.5.3. Clocks
26.5.4. DMA
26.5.5. Interrupts
26.5.6. Events
26.5.7. Debug Operation
26.5.8. Register Access Protection
26.5.9. SAM L11 TrustZone-Specific Register Access Protection
26.5.10. Analog Connections
26.6. Functional Description
26.6.1. Voltage Regulators System Operation
26.6.1.1. Enabling, Disabling, and Resetting
26.6.1.2. Initialization
26.6.1.3. Selecting the Main Voltage Regulator
26.6.1.4. Voltage Scaling Control
26.6.1.5. Sleep Mode Operation
26.6.2. Voltage Reference System Operation
26.6.2.1. Initialization
26.6.2.2. Enabling, Disabling, and Resetting
26.6.2.3. Selecting a Voltage Reference
26.6.2.4. Sleep Mode Operation
26.6.3. Brown-Out Detectors
26.6.3.1. Initialization
26.6.3.2. Enabling, Disabling, and Resetting
26.6.3.3. 3.3V Brown-Out Detector (BOD33)
26.6.3.4. 1.2V Brown-Out Detector (BOD12)
26.6.3.5. Continuous Mode
26.6.3.6. Sampling Mode
26.6.3.7. Hysteresis
26.6.3.8. Sleep Mode Operation
26.6.3.8.1. Standby Mode
26.6.4. Interrupts
26.6.5. Events
26.6.6. Synchronization
26.6.7. Low-Power VREF in Active Mode
26.7. Register Summary
26.8. Register Description
26.8.1. Interrupt Enable Clear
26.8.2. Interrupt Enable Set
26.8.3. Interrupt Flag Status and Clear
26.8.4. Status
26.8.5. 3.3V Brown-Out Detector (BOD33) Control
26.8.6. Voltage Regulator System (VREG) Control
26.8.7. Voltage References System (VREF) Control
26.8.8. Event Control
27. WDT – Watchdog Timer
27.1. Overview
27.2. Features
27.3. Block Diagram
27.4. Signal Description
27.5. Product Dependencies
27.5.1. I/O Lines
27.5.2. Power Management
27.5.3. Clocks
27.5.4. DMA
27.5.5. Interrupts
27.5.6. Events
27.5.7. Debug Operation
27.5.8. Register Access Protection
27.5.9. SAM L11 TrustZone-Specific Register Access Protection
27.5.10. Analog Connections
27.6. Functional Description
27.6.1. Principle of Operation
27.6.2. Basic Operation
27.6.2.1. Initialization
27.6.2.2. Configurable Reset Values
27.6.2.3. Enabling, Disabling, and Resetting
27.6.2.4. Normal Mode
27.6.2.5. Window Mode
27.6.3. DMA Operation
27.6.4. Interrupts
27.6.5. Events
27.6.6. Sleep Mode Operation
27.6.7. Synchronization
27.6.8. Additional Features
27.6.8.1. Always-On Mode
27.6.8.2. Early Warning
27.7. Register Summary
27.8. Register Description
27.8.1. Control A
27.8.2. Configuration
27.8.3. Early Warning Control
27.8.4. Interrupt Enable Clear
27.8.5. Interrupt Enable Set
27.8.6. Interrupt Flag Status and Clear
27.8.7. Synchronization Busy
27.8.8. Clear
28. RTC – Real-Time Counter
28.1. Overview
28.2. Features
28.3. Block Diagram
28.4. Signal Description
28.5. Product Dependencies
28.5.1. I/O Lines
28.5.2. Power Management
28.5.3. Clocks
28.5.4. DMA
28.5.5. Interrupts
28.5.6. Events
28.5.7. Debug Operation
28.5.8. Register Access Protection
28.5.9. SAM L11 TrustZone-Specific Register Access Protection
28.5.10. Analog Connections
28.6. Functional Description
28.6.1. Principle of Operation
28.6.2. Basic Operation
28.6.2.1. Initialization
28.6.2.2. Enabling, Disabling, and Resetting
28.6.2.3. 32-Bit Counter (Mode 0)
28.6.2.4. 16-Bit Counter (Mode 1)
28.6.2.5. Clock/Calendar (Mode 2)
28.6.3. DMA Operation
28.6.4. Interrupts
28.6.5. Events
28.6.6. Sleep Mode Operation
28.6.7. Synchronization
28.6.8. Additional Features
28.6.8.1. Periodic Intervals
28.6.8.2. Frequency Correction
28.6.8.3. General Purpose Registers
28.6.8.4. Tamper Detection
28.6.8.4.1. Timestamp
28.6.8.4.2. Active Layer Protection
28.7. Register Description
28.7.1. Register Summary - Mode 0 - 32-Bit Counter
28.7.2. Register Description - Mode 0 - 32-Bit Counter
28.7.2.1. Control A in COUNT32 mode (CTRLA.MODE=0)
28.7.2.2. Control B in COUNT32 mode (CTRLA.MODE=0)
28.7.2.3. Event Control in COUNT32 mode (CTRLA.MODE=0)
28.7.2.4. Interrupt Enable Clear in COUNT32 mode (CTRLA.MODE=0)
28.7.2.5. Interrupt Enable Set in COUNT32 mode (CTRLA.MODE=0)
28.7.2.6. Interrupt Flag Status and Clear in COUNT32 mode (CTRLA.MODE=0)
28.7.2.7. Debug Control
28.7.2.8. Synchronization Busy in COUNT32 mode (CTRLA.MODE=0)
28.7.2.9. Frequency Correction
28.7.2.10. Counter Value in COUNT32 mode (CTRLA.MODE=0)
28.7.2.11. Compare 0 Value in COUNT32 mode (CTRLA.MODE=0)
28.7.2.12. General Purpose n
28.7.2.13. Tamper Control
28.7.2.14. Timestamp
28.7.2.15. Tamper ID
28.7.2.16. Tamper Control B
28.7.3. Register Summary - Mode 1 - 16-Bit Counter
28.7.4. Register Description - Mode 1 - 16-Bit Counter
28.7.4.1. Control A in COUNT16 mode (CTRLA.MODE=1)
28.7.4.2. Control B in COUNT16 mode (CTRLA.MODE=1)
28.7.4.3. Event Control in COUNT16 mode (CTRLA.MODE=1)
28.7.4.4. Interrupt Enable Clear in COUNT16 mode (CTRLA.MODE=1)
28.7.4.5. Interrupt Enable Set in COUNT16 mode (CTRLA.MODE=1)
28.7.4.6. Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
28.7.4.7. Debug Control
28.7.4.8. Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
28.7.4.9. Frequency Correction
28.7.4.10. Counter Value in COUNT16 mode (CTRLA.MODE=1)
28.7.4.11. Counter Period in COUNT16 mode (CTRLA.MODE=1)
28.7.4.12. Compare n Value in COUNT16 mode (CTRLA.MODE=1)
28.7.4.13. General Purpose n
28.7.4.14. Tamper Control
28.7.4.15. Timestamp
28.7.4.16. Tamper ID
28.7.4.17. Tamper Control B
28.7.5. Register Summary - Mode 2 - Clock/Calendar
28.7.6. Register Description - Mode 2 - Clock/Calendar
28.7.6.1. Control A in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.2. Control B in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.3. Event Control in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.4. Interrupt Enable Clear in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.5. Interrupt Enable Set in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.6. Interrupt Flag Status and Clear in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.7. Debug Control
28.7.6.8. Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.9. Frequency Correction
28.7.6.10. Clock Value in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.11. Alarm Value in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.12. Alarm Mask in Clock/Calendar mode (CTRLA.MODE=2)
28.7.6.13. General Purpose n
28.7.6.14. Tamper Control
28.7.6.15. Timestamp Value
28.7.6.16. Tamper ID
28.7.6.17. Tamper Control B
29. DMAC – Direct Memory Access Controller
29.1. Overview
29.2. Features
29.3. Block Diagram
29.4. Signal Description
29.5. Product Dependencies
29.5.1. I/O Lines
29.5.2. Power Management
29.5.3. Clocks
29.5.4. DMA
29.5.5. Interrupts
29.5.6. Events
29.5.7. Debug Operation
29.5.8. Register Access Protection
29.5.9. SAM L11 TrustZone-Specific Register Access Protection
29.5.10. Analog Connections
29.6. Functional Description
29.6.1. Principle of Operation
29.6.1.1. DMA
29.6.1.2. CRC
29.6.2. Basic Operation
29.6.2.1. Initialization
29.6.2.2. Enabling, Disabling, and Resetting
29.6.2.3. Transfer Descriptors
29.6.2.4. Arbitration
29.6.2.5. Data Transmission
29.6.2.6. Transfer Triggers and Actions
29.6.2.7. Addressing
29.6.2.8. Error Handling
29.6.3. Additional Features
29.6.3.1. Linked Descriptors
29.6.3.1.1. Adding Descriptor to the End of a List
29.6.3.1.2. Modifying a Descriptor in a List
29.6.3.1.3. Adding a Descriptor Between Existing Descriptors
29.6.3.2. Channel Suspend
29.6.3.3. Channel Resume and Next Suspend Skip
29.6.3.4. Event Input Actions
29.6.3.5. Event Output Selection
29.6.3.6. Aborting Transfers
29.6.3.7. CRC Operation
29.6.4. DMA Operation
29.6.5. Interrupts
29.6.6. Events
29.6.7. Sleep Mode Operation
29.6.8. Synchronization
29.7. Register Summary
29.8. Register Description
29.8.1. Control
29.8.2. CRC Control
29.8.3. CRC Data Input
29.8.4. CRC Checksum
29.8.5. CRC Status
29.8.6. Debug Control
29.8.7. Quality of Service Control
29.8.8. Software Trigger Control
29.8.9. Priority Control 0
29.8.10. Interrupt Pending
29.8.11. Interrupt Status
29.8.12. Busy Channels
29.8.13. Pending Channels
29.8.14. Active Channel and Levels
29.8.15. Descriptor Memory Section Base Address
29.8.16. Write-Back Memory Section Base Address
29.8.17. Channel ID
29.8.18. Channel Control A
29.8.19. Channel Control B
29.8.20. Channel Interrupt Enable Clear
29.8.21. Channel Interrupt Enable Set
29.8.22. Channel Interrupt Flag Status and Clear
29.8.23. Channel Status
29.9. Register Summary - SRAM
29.10. Register Description - SRAM
29.10.1. Block Transfer Control
29.10.2. Block Transfer Count
29.10.3. Block Transfer Source Address
29.10.4. Block Transfer Destination Address
29.10.5. Next Descriptor Address
30. EIC – External Interrupt Controller
30.1. Overview
30.2. Features
30.3. Block Diagram
30.4. Signal Description
30.5. Product Dependencies
30.5.1. I/O Lines
30.5.2. Power Management
30.5.3. Clocks
30.5.4. DMA
30.5.5. Interrupts
30.5.6. Events
30.5.7. Debug Operation
30.5.8. Register Access Protection
30.5.9. SAM L11 TrustZone Specific Register Access Protection
30.5.10. Analog Connections
30.6. Functional Description
30.6.1. Principle of Operation
30.6.2. Basic Operation
30.6.2.1. Initialization
30.6.2.2. Enabling, Disabling, and Resetting
30.6.3. External Pin Processing
30.6.4. Additional Features
30.6.4.1. Non-Maskable Interrupt (NMI)
30.6.4.2. Asynchronous Edge Detection Mode (No Debouncing)
30.6.4.3. Interrupt Pin Debouncing
30.6.5. DMA Operation
30.6.6. Interrupts
30.6.7. Events
30.6.8. Sleep Mode Operation
30.6.9. SAM L11 Secure Access Rights
30.6.10. Synchronization
30.7. Register Summary
30.8. Register Description
30.8.1. Control A
30.8.2. Non-Maskable Interrupt Control
30.8.3. Non-Maskable Interrupt Flag Status and Clear
30.8.4. Synchronization Busy
30.8.5. Event Control
30.8.6. Interrupt Enable Clear
30.8.7. Interrupt Enable Set
30.8.8. Interrupt Flag Status and Clear
30.8.9. External Interrupt Asynchronous Mode
30.8.10. External Interrupt Sense Configuration
30.8.11. Debouncer Enable
30.8.12. Debouncer Prescaler
30.8.13. Pin State
30.8.14. Security Attribution Check
30.8.15. Non-secure Interrupt
31. NVMCTRL – Nonvolatile Memory Controller
31.1. Overview
31.2. Features
31.3. Block Diagram
31.4. Signal Description
31.5. Product Dependencies
31.5.1. Power Management
31.5.2. Clocks
31.5.3. Interrupts
31.5.4. Events
31.5.5. Debug Operation
31.5.6. Register Access Protection
31.5.7. SAM L11 TrustZone Specific Register Access Protection
31.5.8. Analog Connections
31.6. Functional Description
31.6.1. Principle of Operation
31.6.1.1. Initialization
31.6.2. Memory Organization
31.6.3. Region Unlock Bits
31.6.4. Command and Data Interface
31.6.4.1. FLASH Read
31.6.4.2. DATA FLASH Read
31.6.4.3. FLASH, DATA FLASH Write
31.6.4.3.1. Procedure for Manual Page Writes (CTRLC.MANW=1)
31.6.4.3.2. Procedure for Automatic Page Writes (CTRLC.MANW=0)
31.6.4.4. Page Buffer Clear
31.6.4.5. Erase Row
31.6.4.5.1. Procedure for Erase Row
31.6.4.6. Set and Clear Power Reduction Mode
31.6.5. NVM Rows Operations
31.6.6. Event Automatic Write
31.6.7. Tamper Erase
31.6.8. Silent Access
31.6.9. Chip Erase
31.6.10. Cache
31.6.11. Debugger Access Level
31.6.12. SAM L11 TrustZone Protection Considerations
31.6.12.1. Page Buffer Clear
31.6.12.2. Page Write
31.6.12.3. Erase Row
31.6.12.4. Lock Regions
31.6.12.5. Cache
31.6.12.6. Data Flash Scrambling
31.6.12.7. Tamper Erase
31.7. Register Summary
31.8. Register Description
31.8.1. Control A
31.8.2. Control B
31.8.3. Control C
31.8.4. Event Control
31.8.5. Interrupt Enable Clear
31.8.6. Interrupt Enable Set
31.8.7. Interrupt Flag Status and Clear
31.8.8. Status
31.8.9. Address
31.8.10. Secure Region Unlock Bits
31.8.11. Non-Secure Region Unlock Bits
31.8.12. NVM Parameter
31.8.13. Data Scramble Control
31.8.14. Security Control
31.8.15. Secure Boot Configuration
31.8.16. Secure Application and Data Configuration
31.8.17. Non-secure Write Enable
31.8.18. Non-secure Write Enable Check
32. TrustRAM (TRAM)
32.1. Overview
32.2. Features
32.3. Block Diagram
32.4. Signal Description
32.5. Product Dependencies
32.5.1. I/O Lines
32.5.2. Power Management
32.5.3. Clocks
32.5.4. DMA
32.5.5. Interrupts
32.5.6. Events
32.5.7. Debug Operation
32.5.8. Register Access Protection
32.5.9. SAM L11 TrustZone-Specific Register Access Protection
32.6. Functional Description
32.6.1. Principle of Operation
32.6.2. Basic Operation
32.6.2.1. Initialization
32.6.2.2. Enabling, Disabling and Resetting
32.6.2.3. Scrambling
32.6.2.4. Silent Access
32.6.2.5. Data Remanence Prevention
32.6.2.6. Tamper Full Erase
32.6.3. Interrupts
32.6.4. Sleep Mode Operation
32.6.5. Synchronization
32.7. Register Summary
32.8. Register Description
32.8.1. Control A
32.8.2. Interrupt Enable Clear
32.8.3. Interrupt Enable Set
32.8.4. Interrupt Flag Status and Clear
32.8.5. Status
32.8.6. Synchronization Busy
32.8.7. Data Scramble Control
32.8.8. Permutation Write
32.8.9. Permutation Read
32.8.10. Security RAM n
33. PORT - I/O Pin Controller
33.1. Overview
33.2. Features
33.3. Block Diagram
33.4. Signal Description
33.5. Product Dependencies
33.5.1. I/O Lines
33.5.2. Power Management
33.5.3. Clocks
33.5.4. DMA
33.5.5. Interrupts
33.5.6. Events
33.5.7. Debug Operation
33.5.8. Register Access Protection
33.5.9. Analog Connections
33.5.10. CPU Local Bus
33.6. Functional Description
33.6.1. Principle of Operation
33.6.2. Basic Operation
33.6.2.1. Initialization
33.6.2.2. Operation
33.6.3. I/O Pin Configuration
33.6.3.1. Pin Configurations Summary
33.6.3.2. Input Configuration
33.6.3.3. Totem-Pole Output
33.6.3.4. Digital Functionality Disabled
33.6.4. SAM L11 Secure Access Rights
33.6.5. Events
33.6.6. PORT Access Priority
33.7. Register Summary
33.8. Register Description
33.8.1. Data Direction
33.8.2. Data Direction Clear
33.8.3. Data Direction Set
33.8.4. Data Direction Toggle
33.8.5. Data Output Value
33.8.6. Data Output Value Clear
33.8.7. Data Output Value Set
33.8.8. Data Output Value Toggle
33.8.9. Data Input Value
33.8.10. Control
33.8.11. Write Configuration
33.8.12. Event Input Control
33.8.13. Peripheral Multiplexing n
33.8.14. Pin Configuration n
33.8.15. Interrupt Enable Clear
33.8.16. Interrupt Enable Set
33.8.17. Interrupt Flag Status and Clear
33.8.18. Security Attribution
33.8.19. Security Attribution Check
34. EVSYS – Event System
34.1. Overview
34.2. Features
34.3. Block Diagram
34.4. Product Dependencies
34.4.1. I/O Lines
34.4.2. Power Management
34.4.3. Clocks
34.4.4. DMA
34.4.5. Interrupts
34.4.6. Events
34.4.7. Debug Operation
34.4.8. Register Access Protection
34.4.9. SAM L11 TrustZone Specific Register Access Protection
34.4.10. Analog Connections
34.5. Functional Description
34.5.1. Principle of Operation
34.5.2. Basic Operation
34.5.2.1. Initialization
34.5.2.2. Enabling, Disabling, and Resetting
34.5.2.3. User Multiplexer Setup
34.5.2.4. Event System Channel
34.5.2.5. Event Generators
34.5.2.6. Channel Path
34.5.2.7. Edge Detection
34.5.2.8. Event Latency
34.5.2.9. The Overrun Channel n Interrupt
34.5.2.10. The Event Detected Channel n Interrupt
34.5.2.11. Channel Status
34.5.2.12. Software Event
34.5.2.13. Interrupt Status and Interrupts Arbitration
34.5.3. Interrupts
34.5.4. Sleep Mode Operation
34.6. Register Summary
34.7. Register Description
34.7.1. Control A
34.7.2. Software Event
34.7.3. Priority Control
34.7.4. Channel Pending Interrupt
34.7.5. Interrupt Status
34.7.6. Busy Channels
34.7.7. Ready Users
34.7.8. Channel n Control
34.7.9. Channel n Interrupt Enable Clear
34.7.10. Channel n Interrupt Enable Set
34.7.11. Channel n Interrupt Flag Status and Clear
34.7.12. Channel n Status
34.7.13. Event User m
34.7.14. Interrupt Enable Clear
34.7.15. Interrupt Enable Set
34.7.16. Interrupt Flag Status and Clear
34.7.17. Channel Security Attribution
34.7.18. Channel Security Attribution Check
34.7.19. Event User Security Attribution
34.7.20. Event User Security Attribution Check
35. SERCOM – Serial Communication Interface
35.1. Overview
35.2. Features
35.3. Block Diagram
35.4. Signal Description
35.5. Product Dependencies
35.5.1. I/O Lines
35.5.2. Power Management
35.5.3. Clocks
35.5.4. DMA
35.5.5. Interrupts
35.5.6. Events
35.5.7. Debug Operation
35.5.8. Register Access Protection
35.5.9. SAM L11 TrustZone-Specific Register Access Protection
35.5.10. Analog Connections
35.6. Functional Description
35.6.1. Principle of Operation
35.6.2. Basic Operation
35.6.2.1. Initialization
35.6.2.2. Enabling, Disabling, and Resetting
35.6.2.3. Clock Generation – Baud-Rate Generator
35.6.2.3.1. Asynchronous Arithmetic Mode BAUD Value Selection
35.6.3. Additional Features
35.6.3.1. Address Match and Mask
35.6.3.1.1. Address With Mask
35.6.3.1.2. Two Unique Addresses
35.6.3.1.3. Address Range
35.6.3.2. Secure Pin Multiplexing (on SERCOM) Pins (SAM L11 Only)
35.6.4. DMA Operation
35.6.5. Interrupts
35.6.6. Events
35.6.7. Sleep Mode Operation
35.6.8. Synchronization
36. SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
36.1. Overview
36.2. USART Features
36.3. Block Diagram
36.4. Signal Description
36.5. Product Dependencies
36.5.1. I/O Lines
36.5.2. Power Management
36.5.3. Clocks
36.5.4. DMA
36.5.5. Interrupts
36.5.6. Events
36.5.7. Debug Operation
36.5.8. Register Access Protection
36.5.9. SAM L11 TrustZone-Specific Register Access Protection
36.5.10. Analog Connections
36.6. Functional Description
36.6.1. Principle of Operation
36.6.2. Basic Operation
36.6.2.1. Initialization
36.6.2.2. Enabling, Disabling, and Resetting
36.6.2.3. Clock Generation and Selection
36.6.2.3.1. Synchronous Clock Operation
36.6.2.4. Data Register
36.6.2.5. Data Transmission
36.6.2.5.1. Disabling the Transmitter
36.6.2.6. Data Reception
36.6.2.6.1. Disabling the Receiver
36.6.2.6.2. Error Bits
36.6.2.6.3. Asynchronous Data Reception
36.6.2.6.4. Asynchronous Operational Range
36.6.3. Additional Features
36.6.3.1. Parity
36.6.3.2. Hardware Handshaking
36.6.3.3. IrDA Modulation and Demodulation
36.6.3.4. Break Character Detection and Auto-Baud/LIN Client
36.6.3.5. RS485
36.6.3.6. ISO 7816 for Smart Card Interfacing
36.6.3.7. Collision Detection
36.6.3.8. Loop-Back Mode
36.6.3.9. Start-of-Frame Detection
36.6.3.10. Sample Adjustment
36.6.4. DMA, Interrupts and Events
36.6.4.1. DMA Operation
36.6.4.2. Interrupts
36.6.4.3. Events
36.6.5. Sleep Mode Operation
36.6.6. Synchronization
36.7. Register Summary
36.8. Register Description
36.8.1. Control A
36.8.2. Control B
36.8.3. Control C
36.8.4. Baud
36.8.5. Receive Pulse Length Register
36.8.6. Interrupt Enable Clear
36.8.7. Interrupt Enable Set
36.8.8. Interrupt Flag Status and Clear
36.8.9. Status
36.8.10. Synchronization Busy
36.8.11. Receive Error Count
36.8.12. Data
36.8.13. Debug Control
37. SERCOM SPI – SERCOM Serial Peripheral Interface
37.1. Overview
37.2. Features
37.3. Block Diagram
37.4. Signal Description
37.5. Product Dependencies
37.5.1. I/O Lines
37.5.2. Power Management
37.5.3. Clocks
37.5.4. DMA
37.5.5. Interrupts
37.5.6. Events
37.5.7. Debug Operation
37.5.8. Register Access Protection
37.5.9. SAM L11 TrustZone-Specific Register Access Protection
37.5.10. Analog Connections
37.6. Functional Description
37.6.1. Principle of Operation
37.6.2. Basic Operation
37.6.2.1. Initialization
37.6.2.2. Enabling, Disabling, and Resetting
37.6.2.3. Clock Generation
37.6.2.4. Data Register
37.6.2.5. SPI Transfer Modes
37.6.2.6. Transferring Data
37.6.2.6.1. Host
37.6.2.6.2. Client
37.6.2.7. Receiver Error Bit
37.6.3. Additional Features
37.6.3.1. Address Recognition
37.6.3.2. Preloading of the Client Shift Register
37.6.3.3. Host with Several Clients
37.6.3.4. Loop-Back Mode
37.6.3.5. Hardware Controlled SS
37.6.3.6. SPI Select Low Detection
37.6.4. DMA, Interrupts, and Events
37.6.4.1. DMA Operation
37.6.4.2. Interrupts
37.6.4.3. Events
37.6.5. Sleep Mode Operation
37.6.6. Synchronization
37.7. Register Summary
37.8. Register Description
37.8.1. Control A
37.8.2. Control B
37.8.3. Baud Rate
37.8.4. Interrupt Enable Clear
37.8.5. Interrupt Enable Set
37.8.6. Interrupt Flag Status and Clear
37.8.7. Status
37.8.8. Synchronization Busy
37.8.9. Address
37.8.10. Data
37.8.11. Debug Control
38. SERCOM I2C – SERCOM Inter-Integrated Circuit
38.1. Overview
38.2. Features
38.3. Block Diagram
38.4. Signal Description
38.5. Product Dependencies
38.5.1. I/O Lines
38.5.2. Power Management
38.5.3. Clocks
38.5.4. DMA
38.5.5. Interrupts
38.5.6. Events
38.5.7. Debug Operation
38.5.8. Register Access Protection
38.5.9. SAM L11 TrustZone-Specific Register Access Protection
38.5.10. Analog Connections
38.6. Functional Description
38.6.1. Principle of Operation
38.6.2. Basic Operation
38.6.2.1. Initialization
38.6.2.2. Enabling, Disabling, and Resetting
38.6.2.3. I2C Bus State Logic
38.6.2.4. I2C Host Operation
38.6.2.4.1. Host Clock Generation
38.6.2.4.1.1. Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
38.6.2.4.1.2. Host Clock Generation (High-Speed Mode)
38.6.2.4.2. Transmitting Address Packets
38.6.2.4.3. Transmitting Data Packets
38.6.2.4.4. Receiving Data Packets (SCLSM=0)
38.6.2.4.5. Receiving Data Packets (SCLSM=1)
38.6.2.4.6. High-Speed Mode
38.6.2.4.7. 10-Bit Addressing
38.6.2.5. I2C Client Operation
38.6.2.5.1. Receiving Address Packets (SCLSM=0)
38.6.2.5.2. Receiving Address Packets (SCLSM=1)
38.6.2.5.3. Receiving and Transmitting Data Packets
38.6.2.5.4. High-Speed Mode
38.6.2.5.5. 10-Bit Addressing
38.6.2.5.6. PMBus Group Command
38.6.3. Additional Features
38.6.3.1. SMBus
38.6.3.2. Smart Mode
38.6.3.3. 4-Wire Mode
38.6.3.4. Quick Command
38.6.4. DMA, Interrupts and Events
38.6.4.1. DMA Operation
38.6.4.1.1. Client DMA
38.6.4.1.2. Host DMA
38.6.4.2. Interrupts
38.6.4.3. Events
38.6.5. Sleep Mode Operation
38.6.6. Synchronization
38.7. Register Summary - I2C Client
38.8. Register Description - I2C Client
38.8.1. Control A
38.8.2. Control B
38.8.3. Interrupt Enable Clear
38.8.4. Interrupt Enable Set
38.8.5. Interrupt Flag Status and Clear
38.8.6. Status
38.8.7. Synchronization Busy
38.8.8. Address
38.8.9. Data
38.9. Register Summary - I2C Host
38.10. Register Description - I2C Host
38.10.1. Control A
38.10.2. Control B
38.10.3. Baud Rate
38.10.4. Interrupt Enable Clear
38.10.5. Interrupt Enable Set
38.10.6. Interrupt Flag Status and Clear
38.10.7. Status
38.10.8. Synchronization Busy
38.10.9. Address
38.10.10. Data
38.10.11. Debug Control
39. TC – Timer/Counter
39.1. Overview
39.2. Features
39.3. Block Diagram
39.4. Signal Description
39.5. Product Dependencies
39.5.1. I/O Lines
39.5.2. Power Management
39.5.3. Clocks
39.5.4. DMA
39.5.5. Interrupts
39.5.6. Events
39.5.7. Debug Operation
39.5.8. Register Access Protection
39.5.9. Analog Connections
39.5.10. SAM L11 TrustZone-Specific Register Access Protection
39.6. Functional Description
39.6.1. Principle of Operation
39.6.2. Basic Operation
39.6.2.1. Initialization
39.6.2.2. Enabling, Disabling, and Resetting
39.6.2.3. Prescaler Selection
39.6.2.4. Counter Mode
39.6.2.5. Counter Operations
39.6.2.5.1. Stop Command and Event Action
39.6.2.5.2. Re-Trigger Command and Event Action
39.6.2.5.3. Count Event Action
39.6.2.5.4. Start Event Action
39.6.2.6. Compare Operations
39.6.2.6.1. Waveform Output Operations
39.6.2.7. Double Buffering
39.6.2.8. Capture Operations
39.6.2.8.1. Event Capture Action on Events or I/Os
39.6.2.8.2. Period and Pulse-Width (PPW/PWP) Capture Action on Events
39.6.2.8.3. Pulse-Width (PW) Capture Action on Events
39.6.3. Additional Features
39.6.3.1. One-Shot Operation
39.6.3.2. Time-Stamp Capture on Events or I/Os
39.6.3.3. Minimum Capture
39.6.3.4. Maximum Capture
39.6.4. DMA Operation
39.6.5. Interrupts
39.6.6. Events
39.6.7. Sleep Mode Operation
39.6.8. Synchronization
39.7. Register Description
39.7.1. Register Summary - 8-bit Mode
39.7.2. Register Description - 8-bit Mode
39.7.2.1. Control A
39.7.2.2. Control B Clear
39.7.2.3. Control B Set
39.7.2.4. Event Control
39.7.2.5. Interrupt Enable Clear
39.7.2.6. Interrupt Enable Set
39.7.2.7. Interrupt Flag Status and Clear
39.7.2.8. Status
39.7.2.9. Waveform Generation Control
39.7.2.10. Driver Control
39.7.2.11. Debug Control
39.7.2.12. Synchronization Busy
39.7.2.13. Counter Value, 8-bit Mode
39.7.2.14. Period Value, 8-bit Mode
39.7.2.15. Channel x Compare/Capture Value, 8-bit Mode
39.7.2.16. Period Buffer Value, 8-bit Mode
39.7.2.17. Channel x Compare Buffer Value, 8-bit Mode
39.7.3. Register Summary - 16-bit Mode
39.7.4. Register Description - 16-bit Mode
39.7.4.1. Control A
39.7.4.2. Control B Clear
39.7.4.3. Control B Set
39.7.4.4. Event Control
39.7.4.5. Interrupt Enable Clear
39.7.4.6. Interrupt Enable Set
39.7.4.7. Interrupt Flag Status and Clear
39.7.4.8. Status
39.7.4.9. Waveform Generation Control
39.7.4.10. Driver Control
39.7.4.11. Debug Control
39.7.4.12. Synchronization Busy
39.7.4.13. Counter Value, 16-bit Mode
39.7.4.14. Period Value, 16-bit Mode
39.7.4.15. Channel x Compare/Capture Value, 16-bit Mode
39.7.4.16. Period Buffer Value, 16-bit Mode
39.7.4.17. Channel x Compare Buffer Value, 16-bit Mode
39.7.5. Register Summary - 32-bit Mode
39.7.6. Register Description - 32-bit Mode
39.7.6.1. Control A
39.7.6.2. Control B Clear
39.7.6.3. Control B Set
39.7.6.4. Event Control
39.7.6.5. Interrupt Enable Clear
39.7.6.6. Interrupt Enable Set
39.7.6.7. Interrupt Flag Status and Clear
39.7.6.8. Status
39.7.6.9. Waveform Generation Control
39.7.6.10. Driver Control
39.7.6.11. Debug Control
39.7.6.12. Synchronization Busy
39.7.6.13. Counter Value, 32-bit Mode
39.7.6.14. Period Value, 32-bit Mode
39.7.6.15. Channel x Compare/Capture Value, 32-bit Mode
39.7.6.16. Period Buffer Value, 32-bit Mode
39.7.6.17. Channel x Compare Buffer Value, 32-bit Mode
40. TRNG – True Random Number Generator
40.1. Overview
40.2. Features
40.3. Block Diagram
40.4. Signal Description
40.5. Product Dependencies
40.5.1. I/O Lines
40.5.2. Power Management
40.5.3. Clocks
40.5.4. DMA
40.5.5. Interrupts
40.5.6. Events
40.5.7. Debug Operation
40.5.8. Register Access Protection
40.5.9. SAM L11 TrustZone-Specific Register Access Protection
40.5.10. Analog Connections
40.6. Functional Description
40.6.1. Principle of Operation
40.6.2. Basic Operation
40.6.2.1. Initialization
40.6.2.2. Enabling, Disabling and Resetting
40.6.3. Interrupts
40.6.4. Events
40.6.5. Sleep Mode Operation
40.6.6. Synchronization
40.7. Register Summary
40.8. Register Description
40.8.1. Control A
40.8.2. Event Control
40.8.3. Interrupt Enable Clear
40.8.4. Interrupt Enable Set
40.8.5. Interrupt Flag Status and Clear
40.8.6. Output Data
41. CCL – Configurable Custom Logic
41.1. Overview
41.2. Features
41.3. Block Diagram
41.4. Signal Description
41.5. Product Dependencies
41.5.1. I/O Lines
41.5.2. Power Management
41.5.3. Clocks
41.5.4. DMA
41.5.5. Interrupts
41.5.6. Events
41.5.7. Debug Operation
41.5.8. Register Access Protection
41.5.9. SAM L11 TrustZone-Specific Register Access Protection
41.5.10. Analog Connections
41.6. Functional Description
41.6.1. Principle of Operation
41.6.2. Operation
41.6.2.1. Initialization
41.6.2.2. Enabling, Disabling, and Resetting
41.6.2.3. Lookup Table Logic
41.6.2.4. Truth Table Inputs Selection
41.6.2.5. Filter
41.6.2.6. Edge Detector
41.6.2.7. Sequential Logic
41.6.3. Events
41.6.4. Sleep Mode Operation
41.7. Register Summary
41.8. Register Description
41.8.1. Control
41.8.2. Sequential Control 0
41.8.3. LUT Control x
42. ADC – Analog-to-Digital Converter
42.1. Overview
42.2. Features
42.3. Block Diagram
42.4. Signal Description
42.5. Product Dependencies
42.5.1. I/O Lines
42.5.2. Power Management
42.5.3. Clocks
42.5.4. DMA
42.5.5. Interrupts
42.5.6. Events
42.5.7. Debug Operation
42.5.8. Register Access Protection
42.5.9. SAM L11 TrustZone-Specific Register Access Protection
42.5.10. Analog Connections
42.5.11. Calibration
42.6. Functional Description
42.6.1. Principle of Operation
42.6.2. Basic Operation
42.6.2.1. Initialization
42.6.2.2. Enabling, Disabling and Resetting
42.6.2.3. Operation
42.6.2.4. Prescaler Selection
42.6.2.5. Reference Configuration
42.6.2.6. ADC Resolution
42.6.2.7. Differential and Single-Ended Conversions
42.6.2.8. Conversion Timing and Sampling Rate
42.6.2.9. Accumulation
42.6.2.10. Averaging
42.6.2.11. Oversampling and Decimation
42.6.2.12. Automatic Sequences
42.6.2.13. Window Monitor
42.6.2.14. Offset and Gain Correction
42.6.2.15. Reference Buffer Compensation Offset
42.6.3. Additional Features
42.6.3.1. Double Buffering
42.6.3.2. Device Temperature Measurement
42.6.4. DMA Operation
42.6.5. Interrupts
42.6.6. Events
42.6.7. Sleep Mode Operation
42.6.8. Synchronization
42.7. Register Summary
42.8. Register Description
42.8.1. Control A
42.8.2. Control B
42.8.3. Reference Control
42.8.4. Event Control
42.8.5. Interrupt Enable Clear
42.8.6. Interrupt Enable Set
42.8.7. Interrupt Flag Status and Clear
42.8.8. Sequence Status
42.8.9. Input Control
42.8.10. Control C
42.8.11. Average Control
42.8.12. Sampling Time Control
42.8.13. Window Monitor Lower Threshold
42.8.14. Window Monitor Upper Threshold
42.8.15. Gain Correction
42.8.16. Offset Correction
42.8.17. Software Trigger
42.8.18. Debug Control
42.8.19. Synchronization Busy
42.8.20. Result
42.8.21. Sequence Control
42.8.22. Calibration
43. AC – Analog Comparators
43.1. Overview
43.2. Features
43.3. Block Diagram
43.4. Signal Description
43.5. Product Dependencies
43.5.1. I/O Lines
43.5.2. Power Management
43.5.3. Clocks
43.5.4. DMA
43.5.5. Interrupts
43.5.6. Events
43.5.7. Debug Operation
43.5.8. Register Access Protection
43.5.9. SAM L11 TrustZone-Specific Register Access Protection
43.5.10. Analog Connections
43.6. Functional Description
43.6.1. Principle of Operation
43.6.2. Basic Operation
43.6.2.1. Initialization
43.6.2.2. Enabling, Disabling and Resetting
43.6.2.3. Comparator Configuration
43.6.2.4. Starting a Comparison
43.6.2.4.1. Continuous Measurement
43.6.2.4.2. Single-Shot
43.6.3. Selecting Comparator Inputs
43.6.4. Window Operation
43.6.5. VDD Scaler
43.6.6. Input Hysteresis
43.6.7. Propagation Delay vs. Power Consumption
43.6.8. Filtering
43.6.9. Comparator Output
43.6.10. Offset Compensation
43.6.11. DMA Operation
43.6.12. Interrupts
43.6.13. Events
43.6.14. Sleep Mode Operation
43.6.14.1. Continuous Measurement during Sleep
43.6.14.2. Single-Shot Measurement during Sleep
43.6.15. Synchronization
43.7. Register Summary
43.8. Register Description
43.8.1. Control A
43.8.2. Control B
43.8.3. Event Control
43.8.4. Interrupt Enable Clear
43.8.5. Interrupt Enable Set
43.8.6. Interrupt Flag Status and Clear
43.8.7. Status A
43.8.8. Status B
43.8.9. Debug Control
43.8.10. Window Control
43.8.11. Scaler n
43.8.12. Comparator Control n
43.8.13. Synchronization Busy
44. DAC – Digital-to-Analog Converter
44.1. Overview
44.2. Features
44.3. Block Diagram
44.4. Signal Description
44.5. Product Dependencies
44.5.1. I/O Lines
44.5.2. Power Management
44.5.3. Clocks
44.5.4. DMA
44.5.5. Interrupts
44.5.6. Events
44.5.7. Debug Operation
44.5.8. Register Access Protection
44.5.9. SAM L11 TrustZone-Specific Register Access Protection
44.5.10. Analog Connections
44.6. Functional Description
44.6.1. Principle of Operation
44.6.2. Basic Operation
44.6.2.1. Initialization
44.6.2.2. Enabling, Disabling and Resetting
44.6.2.3. Enabling the Output Buffer
44.6.2.4. Digital to Analog Conversion
44.6.3. DMA Operation
44.6.4. Interrupts
44.6.5. Events
44.6.6. Sleep Mode Operation
44.6.7. Synchronization
44.6.8. Additional Features
44.6.8.1. DAC as an Internal Reference
44.6.8.2. Data Buffer
44.6.8.3. Voltage Pump
44.6.8.4. Dithering mode
44.7. Register Summary
44.8. Register Description
44.8.1. Control A
44.8.2. Control B
44.8.3. Event Control
44.8.4. Interrupt Enable Clear
44.8.5. Interrupt Enable Set
44.8.6. Interrupt Flag Status and Clear
44.8.7. Status
44.8.8. Data DAC
44.8.9. Data Buffer
44.8.10. Synchronization Busy
44.8.11. Debug Control
45. OPAMP – Operational Amplifier Controller
45.1. Overview
45.2. Features
45.3. Block Diagram
45.4. Signal Description
45.5. Product Dependencies
45.5.1. I/O Lines
45.5.2. Power Management
45.5.3. Clocks
45.5.4. DMA
45.5.5. Interrupts
45.5.6. Events
45.5.7. Debug Operation
45.5.8. Register Access Protection
45.5.9. SAM L11 TrustZone-Specific Register Access Protection
45.5.10. Analog Connections
45.5.11. Other dependencies
45.6. Functional Description
45.6.1. Principle of Operation
45.6.2. Basic Operation
45.6.2.1. Initialization
45.6.2.2. Enabling, Disabling, and Resetting
45.6.3. DMA Operation
45.6.4. Interrupts
45.6.5. Events
45.6.6. Sleep Mode Operation
45.6.7. Synchronization
45.6.8. Configuring the Operational Amplifiers
45.6.9. Standalone Mode
45.6.10. Built-in Modes
45.6.10.1. Voltage Follower
45.6.10.2. Inverting PGA
45.6.10.3. Non-Inverting PGA
45.6.10.4. Cascaded Inverting PGA
45.6.10.5. Cascaded Non-Inverting PGA
45.6.10.6. Two OPAMPs Differential Amplifier
45.6.10.7. Instrumentation Amplifier
45.6.10.8. High Gain Instrumentation Amplifier
45.6.10.9. Transimpedance amplifier
45.6.10.10. Programmable Hysteresis
45.6.11. ADC Driver
45.6.11.1. Buffer/PGA for ADC
45.6.11.2. Offset and Gain Compensation
45.6.11.3. Offset Compensation
45.6.11.4. Gain Compensation
45.6.12. AC Driver
45.6.13. Input Connection to DAC
45.6.14. Reference Buffer (REFBUF)
45.6.15. Voltage Doubler
45.6.16. Performance vs. Power Consumption
45.7. Register Summary
45.8. Register Description
45.8.1. Control A
45.8.2. Status
45.8.3. OPAMP Control x
45.8.4. Resistor Control
46. PTC - Peripheral Touch Controller
46.1. Overview
46.2. Features
46.3. Block Diagram
46.4. Signal Description
46.5. Product Dependencies
46.5.1. I/O Lines
46.5.1.1. Mutual-Capacitance Sensor Arrangement
46.5.1.2. Self-Capacitance Sensor Arrangement
46.5.2. Clocks
46.5.3. SAM L11 TrustZone-Specific Register Access Protection
46.6. Functional Description
47. Electrical Characteristics
47.1. Disclaimer
47.2. Thermal Considerations
47.2.1. Thermal Resistance Data
47.2.2. Junction Temperature
47.3. Absolute Maximum Ratings
47.4. General Operating Ratings
47.5. Supply Characteristics
47.6. Maximum Clock Frequencies
47.7. Power Consumption
47.8. Wake-Up Time
47.9. I/O Pin Characteristics
47.10. Injection Current
47.11. Analog Characteristics
47.11.1. Voltage Regulator Characteristics
47.11.1.1. Buck Converter
47.11.1.2. LDO Regulator
47.11.2. Power-On Reset (POR) Characteristics
47.11.3. Brown-Out Detectors (BOD) Characteristics
47.11.4. Analog-to-Digital Converter (ADC) Characteristics
47.11.5. Digital-to-Analog Converter (DAC) Characteristics
47.11.6. Analog Comparator (AC) Characteristics
47.11.7. DETREF Characteristics
47.11.8. OPAMP Characteristics
47.11.9. Peripheral Touch Controller (PTC) Characteristics
47.12. NVM Characteristics
47.13. Oscillators Characteristics
47.13.1. Crystal Oscillator (XOSC) Characteristics
47.13.2. External 32KHz Crystal Oscillator (XOSC32K) Characteristics
47.13.3. Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
47.13.4. 16 MHz RC Oscillator (OSC16M) Characteristics
47.13.5. Digital Frequency Locked Loop (DFLLULP) Characteristics
47.13.6. Digital Phase Lock Loop (DPLL) Characteristics
47.14. Timing Characteristics
47.14.1. External Reset Pin
47.14.2. SERCOM in SPI Mode in PL0
47.14.3. SERCOM in SPI Mode in PL2
48. 125°C Electrical Characteristics
48.1. Disclaimer
48.2. General Operating Ratings
48.3. Power Consumption
48.4. Analog Characteristics
48.4.1. Brown-Out Detectors (BOD) Characteristics
48.4.2. Analog-to-Digital (ADC) Characteristics
48.4.3. Digital-to-Analog Converter (DAC) Characteristics
48.4.4. Analog Comparator Characteristics
48.4.5. DETREF Characteristics
48.4.6. OPAMP Characteristics
48.4.7. Peripheral Touch Controller (PTC) Characteristics
48.5. Oscillators Characteristics
48.5.1. Crystal Oscillator (XOSC) Characteristics
48.5.2. External 32KHz Crystal Oscillator (XOSC32K) Characteristics
48.5.3. Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
48.5.4. 16 MHz RC Oscillator (OSC16M) Characteristics
48.5.5. Digital Frequency Locked Loop (DFLLULP) Characteristics
48.5.6. Digital Phase Lock Loop (DPLL) Characteristics
48.6. Timing Characteristics
48.6.1. SERCOM in SPI Mode in PL0
48.6.2. SERCOM in SPI Mode in PL2
49. AEC-Q100 Grade (-40°C to 125°C) Electrical Characteristics
49.1. Disclaimer
49.2. General Operating Ratings
49.3. Supply Characteristics
49.4. Power Consumption
49.5. I/O Pin Characteristics
49.6. Analog Characteristics
49.6.1. Brown-Out Detectors (BOD) Characteristics
49.6.2. Analog-to-Digital Converter (ADC) Characteristics
49.6.3. Digital-to-Analog Converter (DAC) Characteristics
49.6.4. Analog Comparator Characteristics
49.6.5. DETREF Characteristics
49.6.6. OPAMP Characteristics
49.6.7. Peripheral Touch Controller (PTC) Characteristics
49.7. NVM Characteristics
49.8. Oscillators Characteristics
49.8.1. Crystal Oscillator (XOSC) Characteristics
49.8.2. External 32 KHz Crystal Oscillator (XOSC32K) Characteristics
49.8.3. Ultra Low-Power Internal 32 kHz RC Oscillator (OSCULP32K) Characteristics
49.8.4. 16 MHz RC Oscillator (OSC16M) Characteristics
49.8.5. Digital Frequency Locked Loop (DFLLULP) Characteristics
49.8.6. Digital Phase Lock Loop (DPLL) Characteristics
49.9. Timing Characteristics
49.9.1. SERCOM in SPI Mode in PL0
49.9.2. SERCOM in SPI Mode in PL2
50. AC and DC Characteristics Graphs
50.1. Typical Power Consumption over Temperature in Sleep Modes - 85°C
50.2. Typical Power Consumption over Temperature in Sleep Modes - 125°C
51. Packaging Information
51.1. Package Marking Information
51.2. Package Drawings
51.2.1. 32-pin TQFP
51.2.2. 24-Pin VQFN
51.2.3. 24-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1)
51.2.4. 32-pin VQFN
51.2.5. 32-pin VQFN with Stepped Wettable Flanks (AEC-Q100 Grade 1)
51.2.6. 24-pin SSOP
51.2.7. 32-pin WLCSP
51.3. Soldering Profile
52. Schematic Checklist
52.1. Introduction
52.2. Power Supply
52.2.1. Power Supply Connections
52.2.1.1. OMEGA-SC_Power_Supply_Connection_LDO
52.2.2. Special Considerations for QFN Packages
52.3. External Analog Reference Connections
52.4. External Reset Circuit
52.5. Unused or Unconnected Pins
52.6. Clocks and Crystal Oscillators
52.6.1. External Clock Source
52.6.2. Crystal Oscillator
52.6.3. External Real Time Oscillator
52.6.4. Calculating the Correct Crystal Decoupling Capacitor
52.7. Programming and Debug Ports
52.7.1. Cortex Debug Connector (10-pin)
52.7.2. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
52.7.3. 20-pin IDC JTAG Connector
52.8. Peripherals Considerations
53. Conventions
53.1. Numerical Notation
53.2. Memory Size and Type
53.3. Frequency and Time
53.4. Registers and Bits
54. Acronyms and Abbreviations
55. Appendix A: Migrating From SAM L21 to SAM L10/L11 (32-pin Package)
55.1. Pinout Differences
55.2. Pinout Multiplexing Differences
55.2.1. SERCOM
55.2.2. CCL
56. Appendix B: Migrating From SAM D20/D21 to SAM L10/L11 (32-pin Package)
56.1. Pinout Differences
56.2. Pinout Multiplexing Differences
56.2.1. EIC
56.2.2. SERCOM (SAM D20)
56.2.3. SERCOM (SAM D21)
56.2.4. TC
56.2.5. GCLK
57. Revision History
58. Legal Disclaimer
The Microchip Web Site
Customer Change Notification Service
Customer Support
Product Identification System
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System Certified by DNV
Worldwide Sales and Service